TheIBAxolotl
The processor and its parts
The central processing unit (CPU) runs program instructions one after another. Three parts do the work:
- Arithmetic logic unit (ALU): performs the actual calculations (addition, subtraction, comparisons) and logical operations (AND, OR, NOT, shifts). The result of a comparison is what lets a program branch.
- Control unit (CU): decodes each instruction and sends control signals that tell the ALU, registers, memory and buses what to do and when. It does not calculate anything itself.
- Registers: tiny, extremely fast storage locations inside the CPU.
| Register | Holds |
|---|---|
| Program counter (PC) | Address of the next instruction to fetch |
| Memory address register (MAR) | Address currently being read from or written to |
| Memory data register (MDR) | Data or instruction just read, or about to be written |
| Current instruction register (CIR) | Instruction being decoded and executed |
| Accumulator (ACC) | Intermediate results from the ALU |
Data moves between the CPU and RAM along the address bus (one direction, CPU to memory), the data bus (both directions) and the control bus (read/write and timing signals).
The fetch-decode-execute cycle
flowchart TD A[Copy PC into MAR] --> B[Read memory at MAR address] B --> C[Instruction arrives in MDR] C --> D[Copy MDR into CIR; PC = PC + 1] D --> E[CU decodes the instruction in CIR] E --> F[Execute: ALU works, memory is read or written, or PC is changed by a jump] F --> A
A jump or loop instruction works by overwriting the PC with a new address during the execute stage, so the next fetch comes from somewhere else.
Memory: speed versus size
Going outward from the CPU, memory gets bigger, cheaper per byte and slower: registers -> cache -> RAM -> secondary storage.
- Cache is small SRAM on or beside the CPU. It keeps copies of recently used and nearby data. Because programs tend to reuse the same data and instructions (loops, arrays), most requests are answered from cache (a cache hit), avoiding the slower trip to RAM. Size alone is not the point: speed and hit rate are.
- RAM is volatile, read-write main memory holding the programs and data in use now.
- ROM is non-volatile and normally read-only. It stores firmware such as the boot instructions, which must survive power-off and must not be changed by accident.
CPU versus GPU
A CPU has a few powerful cores tuned for fast sequential work and complex branching. A GPU has thousands of simpler cores that run the same operation on many pieces of data at once. Rendering pixels and training machine-learning models (huge matrix multiplications) suit a GPU; running an operating system, handling user input or code with lots of if decisions suits a CPU.
Secondary storage
| Type | How it stores | Strengths | Weaknesses |
|---|---|---|---|
| Magnetic (HDD) | Magnetised platters, moving head | Cheap per GB, large | Slow seek, fragile moving parts |
| Solid state (SSD, flash) | Charge in transistor cells | Fast, silent, shock-resistant | Dearer per GB, limited write cycles |
| Optical (DVD, Blu-ray) | Pits read by a laser | Cheap to distribute | Small capacity, slow |
Data compression
- Lossless: the original can be rebuilt exactly. Run-length encoding turns
WWWWWBBBWinto5W3B1W; dictionary methods replace repeated patterns with short codes. Needed for text, code and spreadsheets. - Lossy: discards detail people are unlikely to notice, giving much smaller files (JPEG, MP3, streaming video). The removed data cannot be recovered.
Pipelining in multi-core processors (HL)
Pipelining overlaps stages: while instruction 1 executes, instruction 2 is decoded and instruction 3 is fetched. With \(k\) stages of one cycle each and \(n\) instructions and no stalls:
\[\text{without pipeline} = n \times k \qquad \text{with pipeline} = k + (n - 1)\]
Example: 5 stages, 20 instructions gives 100 cycles without pipelining but 24 with it. Stalls happen when an instruction needs a result not yet produced (data hazard) or after a branch, when already-fetched instructions must be thrown away. Each core of a multi-core CPU has its own pipeline, so independent threads run truly in parallel, but a single sequential task does not speed up just by adding cores.
Common mistakes
- Saying the PC holds the current instruction (it holds the address of the next one).
- Saying the CU performs calculations.
- Explaining cache only by "it is small"; the marks are for speed, proximity and reuse.
- Calling ROM "memory that cannot be changed at all" in modern devices; the key property is non-volatility.
- Forgetting the \(-1\) in the pipeline formula.
Exam tips
- In fetch descriptions, name every register in the order data moves: PC, MAR, memory, MDR, CIR, then the PC increment.
- For "explain why GPU" questions, link many cores to the same operation on lots of independent data.
- For compression, always justify lossless or lossy by what the file is used for.